FIG. 18 is an illustration of a conventional technology for shutting down a power supply, wherein a first circuit block 1503 is connected to a power supply 1501 and also to a ground power supply 1502 by way of a power supply shutdown switch 1506.
A plurality of NMOS transistors constitute the power supply shutdown switch 1506, and the power supply shutdown switch 1506 is turned on and off by a power supply shutdown switch control circuit 1505. The power supply shutdown switch 1506 is turned on when the first circuit block 1503 is operating, while the power supply shutdown switch 1506 is turned off when the first circuit block 1503 is not operating. According to the constitution, the first circuit block 1503 is disconnected from the ground power supply 1502 by the power supply shutdown switch 1506 when the circuit is in a non-operating state.
In the non-operating state, a potential of a pseudo ground power supply 1507 is increased to a level as high as a potential of the power supply 1501 in accordance with a proportion of a leak current of the first circuit block 1503 to a leak current of the power supply shutdown switch 1506, based on which the leak current of the first circuit block 1503 is reduced to at most approximately 1/100 comparing to a leak current in standstill.
Thus, the power supply shutdown technology can largely reduce electric power consumed in LSI when it is applied to a circuit block which does not need to operate and a circuit block which is not required to retain data. The power supply shutdown technology, therefore, is used in, for example, LSIs developed for mobile devices.
When the power supply is repeatedly turned on and off in a short period of time in a plurality of circuit blocks to which the power supply shutdown technology is applied, a noise is generated from the power supply due to a rush current and a resistance of a power supply wire, and the circuit under operating conditions thereby malfunctions. Therefore, it is necessary to reduce a volume of the rush current to such a level that the noise from the power supply does not affect the operating circuit, and it thereby becomes necessary, in the power supply shutdown technology, to control a current flow in the power supply shutdown switch 1506.
When a volume of the current flow in the power supply shutdown switch 1506 is thus controlled, however, such an amount of time for shutting down the power or supplying the power as at least a few μs becomes necessary. This becomes a bottleneck in the pursuit of increasing a system operation speed. FIGS. 19A and 19B illustrate waveforms of a power supply and a waveform of an operation clock at the time of the power supply and power shutdown according to the conventional power supply shutdown technology. FIG. 19A illustrates the operation clock waveform in a slow transient operation in which a few μs of transition time at the time of the power supply and power shutdown is secured in order to control the power supply noise, while FIG. 19B illustrates power supply waveforms VSSV1 and VSSV2 of the pseudo ground power supplies 1507 and 1508 and an operation clock waveform BCLK of the first and second circuit blocks 1503 and 1504 in a fast transient operation in which the transition time at the time of the power supply and power shutdown is reduced to such a level as ns order. FIGS. 19A and 19B illustrate the waveforms in a state where in the circuit block 1503, the power supply/power shutdown is controlled and the circuit block 1504 is an always-ON block and thereafter the circuit blocks 1503 and 1504 are both under operating condition. Further, FIG. 19A illustrates the waveforms in the case where the few μm of transition time at the time of the power supply/power shutdown in the first circuit block 1503 is secured, while FIG. 19B illustrates the waveforms in the case where the transition time at the time of the power supply and power shutdown in the first circuit block 1503 is shortened to such a level as ns order.
As illustrated in FIG. 19A, when an adequate amount of transition time at the time of the power supply and power shutdown is secured, the noise is not generated in the ground power supply 1502 and the pseudo ground power supplies VSSV1 and VSSV2 as well as the first and second circuit blocks 1503 and 1504, but the system operation speedup is hindered.
As illustrated in FIG. 19B, when the transition time at the time of the power supply/power shutdown is shortened, a large noise is generated from the power supply during the transition due to the rush current. Such a power supply noise largely affects the operation of the second circuit block 1504 under operating conditions, resulting in a malfunction of the second circuit block 1504 in the worst case.
The Patent Documents 1 and 2 shown below disclosed a technology wherein the transition time at the time of the power supply and power shutdown is finely adjusted, and a technology wherein the transition time is simply sped up without referring to the noise problem. However, they did not disclose a technology which prevents a generated noise from affecting the circuit under operating conditions.
The Patent Document 3 shown below describes a proposed structure as follows: when the detecting unit detects a functional restart of a functional block in abeyance, a clock signal control unit stops the supply of a clock signal to a functional block under operating conditions during the output period of the predetermined number of clock cycles, and a power supply control unit supplies power to the functional block in abeyance during the clock signal supply stoppage period.    Patent Document 1: H07-264775 of the Japanese Patent Applications Laid-Open    Patent Document 2: H09-321600 of the Japanese Patent Applications Laid-Open    Patent Document 3: US2007/0038876A1